Why Chipmakers Are Moving to Gate-All-Around Transistors

The transistor is the basic switch inside every chip, and its shape has changed only a few times in history. The industry is now in the middle of one of those rare changes. After more than a decade of building leading-edge processors with FinFET transistors, TSMC, Samsung, and Intel are all moving to gate-all-around designs. The reason comes down to physics: the old design is running out of ways to keep electricity under control. For more on the industry behind these chips, see our semiconductor and AI chip coverage.

What a transistor gate does

A transistor works like a valve. Voltage applied to the gate controls whether current flows through the channel beneath or beside it. A good valve shuts tightly when it is off and opens fully when it is on. As transistors shrink, keeping that control gets harder, because the channel is so short that the electric field from the drain can start to push current through even when the gate says stop. That unwanted current is leakage, and it wastes power and generates heat.

The history of transistor design is a series of fixes for this problem. According to a peer-reviewed review of nanosheet reliability, the gate-all-around nanosheet is poised to replace FinFET at 3nm and beyond, and the authors describe it as the second seminal shift in device architecture in the 60-plus-year history of the MOSFET. The first was the move from planar transistors to FinFETs.

Why FinFETs are running out of room

A FinFET raises the channel into a thin vertical fin so the gate can wrap around three sides of it. That was a major improvement, but the design has limits. Synopsys explains that as FinFETs scaled toward 3nm, gate control weakens near the bottom of the fin, closer to the substrate, which makes that area prone to leakage. It adds that FinFET variability increases with continued scaling, making the design less suitable for 2nm and beyond.

There is also a design constraint. Synopsys notes that FinFET width is quantized, meaning it changes in steps based on the number of fins and the space between them in the layout. A secondary technical explainer from Patsnap adds that below gate lengths of roughly 7nm, a three-sided gate can no longer stop the drain’s electric field from penetrating the channel, a failure known as drain-induced barrier lowering. That specific threshold comes from one source, so treat it as an approximation.

How gate-all-around fixes it

A gate-all-around transistor replaces the single fin with stacked horizontal nanosheets, and the gate wraps around every one of them. SemiEngineering summarizes the benefit simply: the gate surrounds the channel on all sides, which gives greater electrostatic control than FinFETs as dimensions shrink and helps suppress leakage and short-channel effects.

The nanosheet review lists several advantages: superior electrostatics, reduced short-channel effects, higher effective device width per footprint, and flexibility to tune power and performance with variable sheet width. Stacking is part of the trick. The Patsnap explainer says that multiple nanosheets act as parallel conduction channels, so effective channel width becomes the number of sheets times the sheet width within the same footprint that used to hold a single fin. In practice, that means more drive current without using more area.

A design knob for chip designers

One underrated benefit is flexibility. Synopsys describes GAA as fins turned sideways and stacked, which makes transistor width continuous in the plane of the layout. Nanosheet width becomes a variable designers can adjust to balance performance against area.

That matters for today’s chips, which mix very different needs on one die. Wider sheets can deliver speed for high-performance blocks, while narrower ones save power and space. For AI processors, where power is the central constraint we described in why AI data centers need much more power, that tuning ability is valuable.

Who is making the move

All three leading manufacturers are involved, each with its own name for the technology. A 2026 overview lists Samsung’s MBCFET, Intel’s RibbonFET, and TSMC’s nanosheets as the main implementations replacing FinFETs at 3nm and below. Samsung was first, introducing GAA at its 3nm node in 2022 according to one node-naming guide, while EE Times notes that TSMC’s N2 is its first GAA node, arriving years after Samsung. We compared the three approaches in the race to build smaller semiconductor nodes.

TSMC’s own results show how fast the shift is happening. In Q2 2026, 2nm accounted for 3 percent of its wafer revenue, only months after N2 production began. The customers are the same ones we covered in why TSMC is so important to the global AI industry: AI accelerator designers and smartphone makers who need more performance per watt.

The cost of the switch

GAA is not free. It is harder to build than FinFET, which we examined in why 2nm chips are more difficult to manufacture. The gate material must fill the tiny gaps between stacked sheets evenly, nanosheet thickness must stay uniform, and new reliability questions arise. The nanosheet review devotes its attention to issues such as the self-heating effect and other degradation mechanisms, which are especially important to understand for future scaling. A separate research paper even examines how gate-to-drain tunneling can add leakage in GAA devices, a reminder that the new design has its own limits.

The payoff also has to be weighed. Analysts quoted by EE Times say N2 brings strong speed and power gains but only a modest density improvement over the previous generation. GAA solves the leakage and control problem, but it doesn’t make shrinking effortless.

What comes after GAA

GAA is likely not the final design. Synopsys describes the next step as complementary FETs, or CFETs, where the n-type and p-type transistors are stacked on top of each other instead of sitting side by side. An academic paper on GAA at 3nm argues that the manufacturing techniques developed for nanosheet stacking will directly inform the transition to CFETs. That is where the industry expects to keep gaining density after nanosheets reach their limits.

The bigger picture

Chipmakers are moving to gate-all-around transistors because FinFETs can no longer control leakage and variability at the smallest sizes, and because AI and mobile chips need more performance per watt. Wrapping the gate around the whole channel restores control, adds drive current in the same area, and gives designers a new way to tune each block. It costs more and is harder to manufacture, but without it, further scaling would stall. Follow our AI hardware coverage to see how GAA performs in real chips and what comes next.