The Race to Build Smaller Semiconductor Nodes

For decades, the chip industry has measured progress by shrinking transistors. Smaller transistors mean more of them on a chip, faster speeds, and lower power use. In 2026 that race has entered a new phase: the leading chipmakers are all bringing so-called 2-nanometer processes to market, and the way they build transistors is changing for the first time in over a decade. For more on the industry behind these chips, see our semiconductor and AI chip coverage.

What a “node” really means

A first caution: the number in a node name no longer describes a physical size. Industry explainers note that names like 3nm, 2nm, and Intel 18A are marketing labels for generations of technology, not measurements of any single feature. Intel’s 18A (18 angstroms) is roughly in the same class as TSMC’s N2 and Samsung’s SF2, even though the names suggest otherwise.

That means comparing nodes by name alone is misleading. The real questions are how many transistors fit in a given area, how fast and efficient they are, how many good chips come out of each wafer (the yield), and what it costs.

The big change: gate-all-around transistors

For years, leading chips used FinFET transistors, where the gate touches the channel on three sides. At 2nm, the industry is moving to gate-all-around designs. According to one 2026 overview, a GAA transistor stacks several horizontal silicon nanosheets with the gate wrapping all the way around each, giving tighter control and lower leakage.

Each company has its own version. Intel calls its design RibbonFET, Samsung uses MBCFET, and TSMC uses nanosheets starting with N2. Samsung moved first on GAA but, according to EE Times, TSMC’s adoption came years later, when it announced production start for N2 at the end of 2025.

The second change: power from the back

The other big innovation is backside power delivery. Chips traditionally route power and signals through the same stack of metal layers above the transistors. Moving the power lines to the back of the wafer frees space for signals and reduces voltage loss.

Here the three leaders have chosen different paths. Intel’s 18A launched with its PowerVia backside power technology built in. TSMC’s N2 does not include backside power, and its Super Power Rail arrives later with A16, which TSMC positions for AI and data center chips. Samsung plans backside power in its SF2Z variant, reportedly in 2027. Sources disagree on whether TSMC’s N2P variant adds backside power, so check TSMC’s own roadmap before stating this in detail.

The contenders

TSMC. The market leader is moving in stages. Analysts quoted by EE Times expect TSMC to lead at 2nm, noting that its GAA arrives first without backside power and that improvements come in later versions. Despite that, TSMC’s strengths are manufacturing scale and ecosystem maturity. In Q2 2026, 2nm already accounted for 3 percent of its wafer revenue, and as we explained in why TSMC is so important to the global AI industry, its capacity effectively sets the pace for the whole AI industry. TechInsights also expects TSMC’s N2 in Apple iPhones before the end of the year.

Intel. Intel has taken the opposite approach, combining GAA and backside power in a single node. According to TechInsights, Intel was first to ship a product combining both, using 18A in its Panther Lake processors. The trade-off is risk: stacking two major changes at once raises yield and schedule challenges, and the same analysis notes it also raises the migration barrier for outside customers.

Samsung. Samsung was first with GAA but has struggled with yields in the past. One roundup says its SF2 process has the Exynos 2600 as its first commercial product, with Samsung claiming gains of 12 percent in performance and 25 percent in power efficiency over its own 3nm process. Those are company claims, not independent measurements.

Rapidus. A fourth entrant is Japan’s Rapidus, targeting 2027 for its 2nm-class technology. TechInsights describes it as a response to growing geopolitical pressure to diversify advanced manufacturing, with yield and ecosystem support still open questions.

Why AI is driving the race

Smaller nodes matter more than ever because AI workloads are limited by power and density. More transistors per area means more compute per chip, and better efficiency means more work per watt, which is the central constraint we described in why AI data centers need much more power. That’s why TSMC’s high-performance computing segment, which covers AI accelerators, already makes up two-thirds of its revenue.

The customers are the same companies we have been following: Nvidia, whose strategy we covered in why Nvidia is expanding beyond GPUs, cloud providers building custom silicon like Microsoft’s Maia, and device makers like Apple. All of them want the best node they can get, which is why lead times are so long. One allocation report estimates 2nm lead times of 78 to 156 weeks with capacity booked into 2028, though that is an analyst estimate.

The gains are getting harder

Shrinking is no longer easy or cheap. EE Times quotes an analyst saying that N2 delivers strong speed and power gains, but its density improvement is mediocre compared with the previous N3E. A more detailed technical review adds that the confined geometry of GAA nanosheets and the introduction of backside power create new manufacturing hurdles, from uniform coating of stacked sheets to heat management.

The tools are changing too. A Data Center Dynamics report says TSMC’s roadmap through 2029 will be manufactured with existing EUV tools without the newest high-NA EUV machines, and another report says TSMC is delaying adoption of the next EUV generation until at least 2029. That points to a practical focus on cost and capacity rather than being first to every new tool.

As transistor shrinking slows, other levers matter more: packaging, memory, and system design. This is why topics like CoWoS and HBM, covered in why semiconductor supply chains matter for AI, have become as important as the node itself.

The bigger picture

The race to smaller nodes is no longer just about a number. It’s about three different strategies for the move from FinFET to gate-all-around and backside power: TSMC staging the changes, Intel combining them, and Samsung betting on early experience. Whoever gets both the technology and the yields right wins the most valuable customers in the world. For the AI industry, the outcome decides how much computing power can be built, and at what cost. Follow our AI hardware coverage as 2nm ramps up and the next nodes take shape.